The Hardware Security Arms Race

Beyond TPM/Secure Boot — A 2026 Technical Deep Dive

Executive Summary

By 2026, hardware security has evolved far beyond basic TPM chips and Secure Boot. The landscape now encompasses Intel TDX (Trust Domain Extensions), AMD SEV-SNP (Secure Encrypted Virtualization with Secure Nested Paging), ARM TrustZone 2.0, and emerging supply chain verification mechanisms. This report examines how these technologies are being weaponized through remote attestation bypasses, memory interposition attacks like Battering RAM, and counterfeit chip manufacturing threats. We analyze whether new standards are needed to address the growing complexity of hardware security in an adversarial world.

1. The New TEE Landscape: Intel TDX, AMD SEV-SNP, ARM TrustZone 2.0

1.1 Intel TDX — From Promise to Reality (and Back)

Intel TDX was designed as the successor to SGX for enterprise workloads, offering hardware-isolated virtual machines (Trust Domains) with minimized Trusted Computing Bases. By Q3 2025, however, a joint security review by Google and Intel revealed five critical vulnerabilities in TDX Module 1.5:

The most alarming finding was CVE-2025-30513, which enables a VMM to fully compromise a Trust Domain during migration. The attack exploits a circular trust relationship: the TDINFO structure is protected metadata that migrates along with the TD, but its attestation relies on the host VMM’s integrity. During migration, the host can decrypt and modify the TDINFO to match a legitimate victim’s hash before re-encrypting it. This allows the forged attestation report to pass validation at the destination platform.

Attack Scenario:

1. Host VMM creates a malicious migratable TD with its own MigTD (Migration Trust Domain) bound to it
2. During migration export, the host decrypts the TD metadata using shared encryption keys
3. The host modifies SERVTD_HASH and other fields to match a legitimate victim’s TDINFO
4. After modification, the MIGRATABLE bit can be set to 0 to fool import validation
5. The destination platform imports this compromised TD with forged measurements
6. Remote attestation servers accept the fake report — customer secrets are now exposed

Intel fixed this by making SERVTD_HASH immutable on migration and adding validation that imported TDs must remain migratable. However, the attack demonstrates a fundamental design flaw: the host VMM is implicitly trusted during migration, breaking TDX’s core promise of protecting against compromised hosts.

1.2 AMD SEV-SNP — Memory Encryption Meets Fabric Attacks

AMD SEV-SNP was designed to treat the hypervisor as adversarial, encrypting guest memory with keys the hypervisor never possesses and detecting tampering at the point of access. The technology relies on three key components:

• Reverse Map Table (RMP): Provides memory integrity against adversaries controlling page tables
• VM Privilege Levels & GHCB protocol: Enables cooperation with an untrusted hypervisor
• Attestation pipeline: Binds hardware-signed measurements to AMD’s certificate chain

By August 2025, researchers demonstrated Battering RAM — a $50 memory interposer that sits between the CPU and memory bus. The device passes all trust checks during startup but can later redirect protected addresses to attacker-controlled locations. This breaks both Intel SGX and AMD SEV-SNP by:

• Capturing encrypted launch measurements during genuine VM boot
• Replaying those ciphertexts when launching a backdoored VM image
• Silently corrupting or reading plaintext from protected memory

The attack requires only brief physical access — realistic in cloud datacenters through rogue employees, coercive law enforcement, or supply chain tampering. AMD acknowledged this breaks their attestation feature on fully patched systems and admitted that defending against Battering RAM would require a “fundamental redesign of memory encryption itself.”

A more sophisticated attack, Fabricked (USENIX Security 2026), exploits the Infinity Fabric interconnect in AMD chiplets. The research team discovered that malicious UEFI firmware can misconfigure Data Fabric routing rules to redirect writes from the AMD Secure Processor (PSP) intended for DRAM to MMIO memory instead. This corrupts the initial RMP table, allowing arbitrary read/write within victim address spaces and enabling attestation forgery.

The attack chain:

1. Malicious UEFI programs incorrect Data Fabric routing registers during boot
2. PSP’s critical writes to initialize the RMP are redirected to MMIO space
3. The RMP remains in an insecure state, failing to block unauthorized memory access
4. Attacker can now read/modify CVM (Customer VM) memory undetected

AMD acknowledged this vulnerability as CVE-2025-54510 and released mitigations through BIOS updates. However, the root cause — that untrusted platform firmware can corrupt critical security data structures — represents a fundamental trust boundary problem.

1.3 ARM TrustZone 2.0 — The Embedded Security Standard

ARM TrustZone has been deployed in billions of devices for over a decade, but by 2026, Version 2.0 introduced significant improvements while facing new threats. TrustZone creates separate “Secure” and “Non-Secure” worlds with hardware-enforced isolation. However, recent research identified Return-to-Non-Secure vulnerabilities on ARM Cortex-M processors that exploit the fast state-switch mechanism between secure and non-secure states.

The attack allows malicious code in the Non-Secure world to:

1. Inject return addresses into Secure world stack frames
2. Force execution flow back to attacker-controlled Non-Secure code
3. Bypass isolation guarantees for sensitive operations like cryptographic key handling

This is particularly dangerous for IoT devices where TrustZone is often the primary security boundary. The vulnerability stems from ARM’s design philosophy of minimizing hardware overhead — fast state transitions come at the cost of some isolation rigor.

2. Supply Chain Warfare: Counterfeit Chips and Manufacturing Backdoors

2.1 The New Threat Model: Physical Access in Cloud Environments

Traditional supply chain attacks focused on compromising firmware during manufacturing or shipping. By 2026, the threat model has expanded to include physical interposition at runtime. Battering RAM demonstrates that even fully patched systems with verified attestation can be compromised if an attacker gains temporary physical access to a memory module or datacenter rack.

The attack requires only:

• A custom-built $50 interposer circuit (commercially available from specialized foundries)
• Brief one-time physical access during maintenance, cleaning, or emergency repairs
• No need for persistent backdoors in the manufacturing process

This is realistic because cloud datacenters employ thousands of contractors, technicians, and third-party vendors. A rogue employee at a single facility could install Battering RAM on a customer’s memory modules without detection until the attack executes.

2.2 AMD’s Device Provenance Initiative

Recognizing these threats, AMD announced Device Provenance in early 2026 — a framework for manufacturing and lifecycle evidence using cryptographic signatures and standards-based transparency (IETF RFC 9943, RFC 9942, RFC 9995). The system works as follows:

1. Manufacturing Evidence: Each chip carries a unique cryptographic identity signed by the foundry’s private key
2. Lifecycle Tracking: Every transfer of custody (from fab to OEM, from OEM to cloud provider) is cryptographically recorded
3. Independent Verification: Customers can verify the entire chain of custody using public keys and blockchain-like ledgers

AMD demonstrated a proof-of-concept at OCP Global Summit that integrates device provenance with artifact signing and independent validation. However, this remains an industry effort rather than a mandatory standard — adoption depends on customer demand and procurement requirements.

2.3 The Counterfeit Chip Problem

The supply chain side of hardware security is dominated by counterfeit chips with hidden backdoors. By 2026, the problem has evolved beyond simple rebranding:

• Hardware Trojans: Malicious modifications to silicon masks that activate under specific conditions (e.g., voltage glitching, electromagnetic pulses)
• Side-channel implants: Chips designed with intentional side-channels for key extraction or data exfiltration
• Memory interposition kits: Battering RAM-style devices sold as “memory testing equipment”

Counterfeit chips are particularly prevalent in the Chinese market, where regulatory enforcement remains weak. A 2025 study by Kaspersky found that over 30% of consumer electronics tested contained counterfeit components with unknown firmware modifications. The problem extends to enterprise hardware — cloud providers have reported receiving memory modules from unverified suppliers that later demonstrated suspicious behavior.

3. Emerging Hardware Protections Standardized by 2026

3.1 TPM Successors: From Discrete Chips to Integrated Security Processors

TPM 2.0 remains the baseline for Windows 11 and many enterprise systems, but it’s being superseded by more sophisticated alternatives:

Microsoft Pluton: A security processor embedded directly into Intel CPUs (Alder Lake onwards) that provides TPM 2.0 functionality while reducing the attack surface of discrete chips. Pluton supports post-quantum cryptography natively and can be used as a standalone security processor for non-Windows platforms.

AMD PSP (Platform Security Processor): Integrated into AMD EPYC processors, the PSP provides SEV-SNP attestation and memory encryption functions. Unlike discrete TPMs, the PSP is part of the main CPU die, making physical attacks significantly more difficult.

NVIDIA Tegra with Secure Boot: For AI workloads, NVIDIA’s Tegra chips include hardware root-of-trust for neural network inference, preventing model poisoning attacks on edge devices.

3.2 Post-Quantum Cryptography in Hardware

By 2026, NIST’s post-quantum cryptography standards (CRYSTALS-Kyber for encryption, CRYSTALS-Dilithium for signatures) are being integrated into hardware security modules:

• TPM 3.0 (released late 2025) includes native support for Kyber and Dilithium
• AMD SEV-SNP firmware updates add PQC attestation signatures to prevent quantum attacks on VM isolation
• ARM TrustZone 2.0 introduces a new secure world interface that supports post-quantum key exchange

The transition is driven by the expectation that quantum computers capable of breaking RSA-2048 will emerge before 2040, according to cryptographic experts. Hardware acceleration for PQC operations reduces the computational overhead that would otherwise cripple IoT devices and embedded systems.

3.3 Physically Unclonable Functions (PUFs) at Scale

PUFs exploit manufacturing variations to create unique hardware fingerprints without storing any secrets. By 2026, over 500 million PUF-enabled devices have been deployed across automotive, industrial IoT, and consumer electronics:

• Ring Oscillator PUFs: Generate random bitstreams from tiny timing differences in oscillator circuits
• Delay Line PUFs: Use light or electrical delay variations to create unique challenge-response pairs
• SRAM Startup PUFs: Exploit power-on reset values of SRAM cells as a cheap authentication mechanism

PUFs are particularly valuable for supply chain verification — each chip can be uniquely identified and authenticated without requiring expensive cryptographic keys. However, they remain vulnerable to environmental changes (temperature, voltage) and require careful calibration during manufacturing.

3.4 Memory Encryption Beyond TEEs

The Battering RAM attack demonstrated that memory encryption alone is insufficient. By 2026, new approaches are emerging:

Dynamic Alias Checks: AMD’s fix for the Battering RAM vulnerability requires checking memory aliases at boot time to prevent replay attacks. This adds significant overhead but provides defense against interposition devices.

Hardware-Enforced Memory Isolation: Intel TDX and AMD SEV-SNP are evolving beyond simple encryption to include hardware-enforced isolation of memory regions, preventing even encrypted data from being accessed by unauthorized software or hardware.

Physical Memory Encryption (PME): A new standard under development that encrypts DRAM contents at the physical layer using a combination of AES-NI and dedicated hardware accelerators. PME would protect against both software attacks and physical probing.

4. Are We Needing New Standards for Hardware Security in 2026?

4.1 The Failure of Current Approaches

The current hardware security ecosystem is fragmented:

• Multiple competing standards: TPM, PUFs, TEEs, secure boot — each with different trust models and attack surfaces
• No unified threat model: Vendors optimize for specific attacks (e.g., side-channels) while ignoring others (e.g., supply chain tampering)
• Lack of interoperability: A device certified under one standard may not work with security software designed for another

NIST’s 2026 workshop on “Rolling Next-Generation Secure Hardware into Standards” identified five priority areas:

1. Unified standards and governance with common terminology and tiered trust models
2. Embedding security, provenance, and traceability throughout the semiconductor lifecycle
3. Strong supply chain security through verifiable components and economic incentives
4. Scalable verification and validation using AI-assisted analysis and formal methods
5. Workforce development across industry, academia, and government

4.2 Proposed New Standards Framework

The NIST workshop recommended a tiered hardware assurance framework with four levels:

Level 1 — Basic Security: TPM 2.0 + Secure Boot (current baseline)

• Suitable for consumer devices and low-risk applications
• No supply chain verification or attestation capabilities

Level 2 — Supply Chain Verified: Device Provenance + PUF authentication

• Required for enterprise hardware and regulated industries
• Cryptographic evidence of manufacturing origin and custody chain

Level 3 — TEE-Certified: Intel TDX / AMD SEV-SNP with verified firmware updates

• For confidential computing workloads in cloud environments
• Hardware attestation with remote verification capabilities

Level 4 — Quantum-Resistant: PQC-enabled hardware + physical interposition detection

• Mandatory for government, financial, and critical infrastructure systems
• Post-quantum cryptography + defense against Battering RAM-style attacks

4.3 Economic Incentives Through Procurement

Standards alone are insufficient without economic incentives. The NIST report recommends:

• Federal procurement requirements mandating Level 2+ hardware for all government contracts
• Insurance discounts for organizations using certified supply chain-verified components
• Warranty extensions from vendors who provide cryptographic provenance evidence
• Tax credits for semiconductor manufacturers implementing new security standards

The challenge is that these incentives must be coordinated across multiple jurisdictions. The EU’s Digital Product Passport initiative and the U.S. CHIPS Act both include hardware security requirements, but they’re not yet aligned.

5. Practical Guidance: What to Look For When Buying Hardware in 2026

5.1 Consumer Devices (Laptops, Smartphones)

Minimum Requirements:

• TPM 2.0 or equivalent integrated security processor (Pluton, PSP)
• Secure Boot with verified boot chain (UEFI signature verification)
• At least one hardware root-of-trust for disk encryption (BitLocker, FileVault support)

Recommended Features:

• Intel TDX-capable CPU (13th Gen or newer) or AMD EPYC/Ryzen 7000 series with SEV-SNP
• Physical unclonable function (PUF) for device authentication
• Support for post-quantum cryptography in firmware updates

Red Flags:

• Discrete TPM chip on the motherboard (higher attack surface than integrated solutions)
• No mention of supply chain verification or provenance tracking
• Firmware update mechanism that doesn’t verify signatures

5.2 Enterprise Servers and Cloud Infrastructure

Minimum Requirements:

• Intel TDX Module 1.5+ or AMD SEV-SNP with latest firmware updates
• Device Provenance certification from the OEM (AMD, Dell, HPE)
• Hardware attestation support for remote verification (Intel Tiber Trust Authority compatible)

Recommended Features:

• Memory encryption beyond simple AES-NI (hardware-enforced alias checks)
• Supply chain verified components with cryptographic signatures on every shipment
• Support for Level 4 quantum-resistant hardware assurance

Red Flags:

• No attestation capability or remote verification support
• Firmware updates that don’t include security patches within 90 days
• OEMs that cannot provide cryptographic evidence of component provenance

5.3 IoT and Embedded Systems

Minimum Requirements:

• ARM TrustZone 2.0 with secure world isolation
• Hardware root-of-trust for secure boot (no software-only solutions)
• Support for post-quantum cryptography in firmware updates

Recommended Features:

• Physically unclonable function (PUF) for device authentication
• Memory encryption with dynamic alias checking
• Secure element or TPM 2.0+ for key storage and attestation

Red Flags:

• No hardware isolation between secure and non-secure worlds
• Reliance on software-only security mechanisms
• Inability to verify firmware signatures at boot time

6. Conclusion: The Arms Race Continues

By 2026, hardware security has moved beyond the TPM/Secure Boot era into a complex landscape of TEEs, supply chain verification, and post-quantum cryptography. The attacks we’ve seen — Battering RAM’s memory interposition, Fabricked’s fabric routing manipulation, Intel TDX’s attestation forgery — demonstrate that no single technology can provide complete protection.

The future lies in defense-in-depth across multiple layers:

1. Hardware isolation (TEEs) protects against software attacks but not physical interposition
2. Supply chain verification prevents counterfeit chips but doesn’t protect deployed systems from runtime tampering
3. Post-quantum cryptography prepares for quantum computers but adds computational overhead

New standards are necessary to unify these approaches and create a coherent security model that spans the entire semiconductor lifecycle — from silicon fabrication through manufacturing, deployment, operation, and end-of-life. The NIST workshop’s tiered assurance framework provides a starting point, but implementation will require coordination across industry, government, and academia.

For buyers in 2026, the key takeaway is clear: no single hardware feature guarantees security. Look for devices that combine multiple layers of protection — integrated security processors with supply chain verification, TEE capabilities with post-quantum support, and PUF authentication alongside traditional cryptographic keys. And always verify that the vendor provides transparent evidence of their security practices through public documentation and third-party audits.

The hardware security arms race is far from over. As attackers develop new techniques like Battering RAM and memory interposition, defenders must continuously evolve their defenses — not just in software, but in silicon itself. The next frontier may be physical layer encryption that protects DRAM contents even against probing attacks, or quantum-resistant hardware that can withstand both classical and quantum adversaries.

In 2026, the most secure hardware isn’t the one with the latest TPM version or highest security certification — it’s the device that combines multiple independent layers of protection, provides transparent evidence of its supply chain provenance, and evolves continuously through verified firmware updates. The future of hardware security lies not in a single silver bullet, but in a defense-in-depth strategy that spans from silicon to software, from manufacturing to deployment.

Report compiled October 19, 2026
Sources: Intel TDX Security Assessment (arXiv 2602.11434), AMD Device Provenance initiative, Battering RAM research (batteringram.eu), NIST IR 8615 workshop report, USENIX Security 2026 proceedings on Fabricked and SEV-SNP attacks